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PD- 97108
IP1203PBF
Single Output Full Function Synchronous Buck Power Block
Features
* * * * * * * * * * 5.5V to 13.2V Input Voltage 0.8V to 8V Output Voltage 15A Maximum Load Capability 200-400kHz Nominal Switching Frequency Over Current Hiccup External Synchronization Capable Overvoltage Protection Over Temperature Protection Internal Features Minimize Layout Sensitivity Very Small Outline 9mm x 9mm x 2.3mm
Integrated Power Semiconductors, PWM Control & Passives
IP1203PBF Power Block
Description The IP1203PBF is a fully optimized solution for medium current synchronous buck applications requiring up to 15A. It includes full function PWM control, with optimized power semiconductor chipsets and associated passives, achieving high power density. Very few external components are required to create a complete synchronous buck power supply. iPOWIRTM technology offers designers an innovative space-saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. IP1203PBF Simplified Application Schematic
VIN
Pin Number (See Page 18) 1, 23
2,3,4,5,7,17,20,21
Pin Name VIN PGND VCC_bypass SS CC FB FBs RT PGOOD VREF SYNC OCSET VSW VSWs VINs
Pin Description Input voltage connection pins Power Ground pins PWM controller power supply pin. Internally generated. Requires a 2.2f external bypass capacitor Soft start pin. External capacitor provides soft start. Pulling soft start pin low will disable the output. Cannot be cycled to unlatch OVP trip Output of the error amplifier Inverting input of the error amplifier Output overvoltage sense pin. Switching frequency setting pin. For RT selection, refer to Fig.9 of the datasheet Power Good pin. Open collector, requires external pulll-up. If function not needed, pin can be left floating Non inverting input of the error amplifier (reference Voltage pin). Connect a 100pF cap from this pin to PGND. External Clock synchronization pin. Set free running frequency to 80% of the SYNC frequency. When not in use, leave pin floating Output overcurrent trip threshold pin Output inductor connection pins Test pad, for internal use, short to VSW Test pad, for internal use, short to VIN
V IN
OC
VOUT
V CC_bypass
6 8 9 10 11
V SW
FB FB S
PGOOD SS
iP1203 IP1203PBF
CC
RT
12 13 14 15 16
PGND
SYNC
V REF
PACKAGE DESCRIPTION
INTERFACE CONNECTION
PARTS PARTS PER PER BAG REEL
T&R ORIENTATION
18,19 22
IP1203PBF iP1203TRPbF
LGA LGA
10 ---
--1000
Fig 26
24
8/11/06
IP1203PBF
Parameter VIN Feedback Output Overvoltage Sense PGOOD Soft Start SYNC Output RMS Current Block Temperature
All specifications @ 25C (unless otherwise specified)
Symbol VIN FB FBS SS IoutVSW TBLK Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Typ Max 15 6 6 15 6 6 15 125 Units Conditions
Absolute Maximum Ratings
--- --- --- --- --- --- --- ---
V
---
-10
A C
See Fig.3
Recommended Operating Conditions
Parameter Input Voltage Range Output RMS Current Symbol VIN IoutVSW Min 5.5 Typ
--- --- --- --- ---
Max 13.2 15 11 8.0 3.3
Units V A A V
Conditions
TPCB = TCASE = 90C. See Fig.3 TPCB = 90C, TCASE = no airflow, no heatsink. For VIN = 12V For VIN = 5.5V
--- ---
Output Voltage Range VOUT 0.8 0.8
Electrical Specifications @ VIN = 12V
Parameter Power Loss Over Current Shutdown HICCUP Duty Cycle Soft Start Time Reference Voltage VOUT Accuracy Error Amplifier Source/Sink Current Error Amplifier Transconductance Output Overvoltage Shutdown Threshold PGOOD Trip Threshold PGOOD Output Low Voltage Symbol PLOSS IOC DHICCUP tSS VREF VOUT_ACC1 VOUT_ACC2 IERR gm OVP VTh_PGOOD VLO_PGOOD Min --- Typ 3.75 25 5 5 0.8 Max 4.9 Units W A % ms V % A mho V V V
FB ramping down ISINK=2mA TBLK = -10C to 125C VIN= 12V, VOUT = 1.5V TBLK = 0C to 70C VIN= 12V, VOUT = 1.5V VIN = 12V, VOUT = 1.5V, CSS=0.1F
Conditions
fSW = 300kHz, VIN = 12V, TBLK= 25C VOUT = 1.5V, IOUT = 15A, See Fig.10 VIN = 12V, VOUT = 1.5V fSW = 300KHz, ROCSET = 40.2k
--- --- --- ---
-3 -2
--- --- --- ---
3 2
--- ---
60 2000
--- ---
--- ---
1.1 x VOUT 1.15 x VOUT 1.2 x VOUT
--- ---
0.85 x VOUT
---
0.3
---
2
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IP1203PBF
Electrical Specifications (continued)
Parameter Frequency SYNC Frequency Range SYNC Pulse Duration SYNC, High Level Threshold Voltage SYNC, Low Level Threshold Voltage VIN Quiescent Current Thermal Shutdown Max Duty Cycle VIN Undervoltage Lockout Threshold Voltage VIN Undervoltage Lockout Hysteresis Output Disable Voltage Soft Start Low Threshold Voltage Input Voltage Slew Rate Symbol fSW fSYNC tSYNC Min 170 255 340 480 Typ
--- --- --- ---
200
Max 230 345 460 800
Units kHz kHz kHz kHz ns V V mA C % V V V mV/s
Conditions
RT = 48.7k RT = 30.9k RT = 21.5k Free running frequency set 20% below sync frequency
---
2
--- ---
0.8 35
--- ---
25 140
---
IIN-LEAKAGE Tempshdn DMAX VIN-UVLO VIN-UVLO HYST VSS-DIS VIN-SLEW
--- ---
85
VIN = 12V
---
4.5 0.25
--- --- --- ---
0.25 50
fSW = 200kHz, TBLK = 25C VIN ramping up to 12V VIN ramp up and ramp down
--- --- --- ---
--- ---
SS Pin Pulled Low
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IP1203PBF
4
VIN 25uA
Bias Generator
SS 3uA
UVLO
V bypass CC
SW1
64uA
OC Latch / Hiccup
Driver
VSW SW2 20k
Control
0.8V
R Q S
25k PWM
Error Amp
PWM Comp OCSET
FB Ramp
25k
CC
Oscilator
PGND
Fig. 1: IP1203PBF Internal Block Diagram
PGood (-10%) OVP (+15%)
SYNC
RT
VREF
0.8V PGOOD SW1 SW2
FBS
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IP1203PBF
6 VIN = 12V VOUT = 1.5V fsw L = 300kHz = 1.0H
5
Power Loss (W)
4
TBLK = 125C
Maximum
3
Typical
2
1
0 0 5 Output Current (A) 10 15
Fig. 2: Power Loss vs. Current
Case Temperature (C)
0
16 14 12
Output Current (A)
10
20
30
40
50
60
70
80
90
100
110
120
130
10 8 6 4 2 0 0
VIN = 12V V OUT = 1.5V fsw L = 300kHz = 1.0H
Safe Operating Area
Tx
10
20
30
40
50
60
70
80
90
100
110
120
130
PCB Temperature (C)
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Fig. 3: Safe Operating Area (SOA) vs. TPCB & TCASE
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IP1203PBF
Typical Performance Curves
1.06
Power Loss (Normalized)
1.5
1.02 1.00 0.98 0.96 5 6
fsw = 300kHz L = 1.0H TBLK = 125C
Power Loss (Normalized)
1.04
VOUT = 1.5V IOUT = 15A
1.36 1.32 1.28 1.24 1.20 1.16 1.12 1.08 1.04 1.00 0.96 0.92 0.8 1.6 2.4 3.2 4.0 4.8 VIN = 12V IOUT = 15A fsw = 300kHz L = 1.0H TBLK = 125C 5.6 6.4 7.2 8.0
SOA Temp Adjustment (C)
10 9
SOA Temp Adjustment (C)
1.0
8 7 6 5 4 3 2 1 0 -1 -2
0.5
0.0
-0.5
-1.0
7
8
9
10
11
12
13
14
Input Voltage (V)
Output Voltage (V)
Fig. 4: Normalized Power Loss vs. VIN
1.120
Power Loss (Normalized)
Fig. 5: Normalized Power Loss vs. VOUT
1.5
Power Loss (Normalized)
1.24 1.20 1.16 1.12 1.08 1.04 1.00 0.96 0.4 0.8 1.2
SOA Temp Adjustment (C)
1.080
VIN = 12V VOUT = 1.5V IOUT = 15A L = 1.0H TBLK = 125C
VIN = 12V VOUT = 1.5V IOUT = 15A fsw = 300kHz TBLK = 125C
6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0
SOA Temp Adjustment (C)
1.0
1.040
0.5
1.000
0.0
0.960 200 250 300 350 400 Swiching Frequency (kHz)
-0.5
1.6
2.0
2.4
Output Inductance (H)
Fig. 6: Normalized Power Loss vs. Frequency
55
ROC-SET (kOhms) for 12Vin
Fig. 7: Normalized Power Loss vs. Inductance
400
Switching Frequency (kHz)
50 45 40 35 30 25 20 15 10 5 6
VOUT = 1.5V fsw = 300kHz L = 1.0H TBLK = 125C
Vin = 12V Vin = 5.5V
205 185 165 145 125 105 85 65 45 25 5
24
ROC-SET (kOhms) for 5.5Vin
380 360 340 320 300 280 260 240 220 200 20 25 30 35 40 RT (kOhms) 45 50
8
10
12 14 16 18 Overload Current (A)
20
22
6
Fig. 8: Nominal Overcurrent Threshold Setting External Resistor Selection
Fig. 9: Switching Frequency vs RT www.irf.com
IP1203PBF
Applying the Safe Operating Area (SOA) Curve
The SOA graph incorporates power loss and thermal resistance information in a way that allows one to solve for maximum current capability in a simplified graphical manner. It incorporates the ability to solve thermal problems where heat is drawn out through the printed circuit board and the top of the case.
0 10 20 30 40 50 60 70 80 90 100 110 120
Procedure
1) Draw a line from Case Temp axis at TCASE to the PCB Temp axis at TPCB. 2) Draw a vertical line from the TX axis intercept to the SOA curve. (see AN-1047 for further explanation of TX ) 3) Draw a horizontal line from the intersection of the vertical line with the SOA curve to the Y axis. The point at which the horizontal line meets the y-axis is the SOA current. 4) If no top sided heatsinking is available, assume TCASE temperature of 125C for worst case performance.
Case Temperature (C)
16
14
1
12
Output Current (A)
10
3
2
8
6
TX
4
2
VIN = 12V VOUT = 1.5V fSW = 300kHz L=1.0uH
iP1203 SOA
0 0 10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (C)
Adjusting the Power Loss and SOA Curves for Different Operating Conditions
To make adjustments to the power loss curves in Fig. 2, multiply the normalized value obtained from the curves in Figs. 4, 5, 6 or 7 by the value indicated on the power loss curve in Fig. 2. Then if multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 2. The resulting product is the final power loss based on all factors. See example no. 1. To make adjustments to the SOA curve in Fig. 3, determine your maximum PCB Temp & Case Temp at the maximum operating current of each IP1203PBF. Then, add the correction temperature from the normalized curves in Figs. 4, 5, 6 or 7 to the TX axis intercept (see procedure no. 2 above) in Fig. 3. When multiple adjustments are required, add all of the temperatures together, then add the sum to the TX axis intercept in Fig. 3. See example no. 2. Operating Conditions for the following examples: Output Current = 12A Output Voltage = 1.2V Input Voltage = 13.2V Sw Freq= 400kHz Inductor = 0.6H
Example 1) Adjusting for Maximum Power Loss: (Fig. 2) Maximum power loss = 4.1W (Fig. 4) Normalized power loss for input voltage 1.025 (Fig. 5) Normalized power loss for output voltage 0.97 (Fig. 6) Normalized power loss for frequency 1.08 (Fig. 7) Normalized power loss for inductor value 1.08 Adjusted Power Loss = 4.1 x 1.025 x 0.97 x 1.08 x 1.08 4.75W
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IP1203PBF
Example 2) Adjusting for SOA Temperature: Assuming TCASE = 110C & TPCB = 90C for both outputs Output1 (Fig. 4) Normalized SOA Temperature for input voltage +0.7C (Fig. 5) Normalized SOA Temperature for output voltage -0.75C (Fig. 6) Normalized SOA Temperature for frequency +1.0C (Fig. 7) Normalized SOA Temperature for inductor value +2.0C TX axis intercept temp adjustment = +0.5C - 0.75C + 1.0C +2.0C +2.75C The following example shows how the SOA current is adjusted for a TX change of +2.75C and output is in SOA
0 10 20 30 40 50 60 70 80 90 100 110 120
Case Temperature (C)
16
14
Unadjusted SOA curve
12
Adjusted SOA curve
Output Current (A)
10
8
6
TX
4
2
VIN = 12V VOUT = 1.5V fSW = 300kHz L=1.0uH
iP1203 SOA IP1203PBF SOA
0 0 10 20 30 40 50 60 70 80 90 100 110 120
PCB Temperature (C)
Iin Average
A
PIN= V Average x I IN Average IN Vin DC P = VOUT Average xI OUTAverage OUT PLoss = PIN - P OUT Iout Average
V
Vin Average
Cin
VIN
VSW
Lo Co
A
Vout Iout
IP1203PBF iP1203
FB
PGND
Averaging Circuit
V
Vout Average
Fig. 10: Power Loss Test Circuit 8 www.irf.com
IP1203PBF
VINs VIN VCCbypass VIN VSWs PGND SS VSW PGND PGND CC FB FBS OCSET SYNC PGND VREF RT PGOOD PGND PGND PGND PGND
VSW
Fig. 11: Recommended PCB Footprint (Top View) www.irf.com 9
IP1203PBF
IP1203PBF Users Design Guidelines
The IP1203PBF is a single output 15A power block consisting of optimized power semiconductors, PWM control and its associated passive components. It is based on a synchronous buck topology and offers an optimized solution where space, efficiency and noise caused by parasitics are of concern. The power block operates with fixed frequency voltage mode control. The IP1203PBF components are integrated in a land grid array (LGA) package. VIN / Enabling the Output The input operating voltage range of the IP1203PBF is 5.5V to 13.2V. The IP1203PBF output is turned on upon application of input voltage. The VIN slew rate should not exceed 50mV/s. The converter can also be turned on and off by releasing or pulling the SS pin low through a logic level MOSFET, the drain of which connects to the soft start pin (see Fig.12). This feature can be useful if sequencing or different start-up timing of different system outputs are required. In situations where the output has undergone a latched shutdown due to overvoltage, cycling Vin will reset the output. Cycling soft start pin will not unlatch the output. Soft Start The Soft Start function provides a controlled rise of the output voltage, thus limiting the inrush current. The soft start function has an internal 25A +/-20% current source that charges the external soft start capacitor Css up to 3V. During power-up, the output voltage starts ramping up only after the charging voltage across the Css capacitor has reached a 0.8Vtyp threshold, as shown in Fig. 13. Fig.12: Soft Start/Enable Circuit
3V
Iss SS 10 10 iP1203 IP1203PBF Css
0.8Vtyp VCss VOUT
Fig. 13: Power Up Threshold Frequency and Synchronization The operating switching frequency (fSW) range of IP1203PBF is 200 kHz to 400 kHz. The desired frequency is set by placing an external resistor to the RT pin of the IP1203PBF. See Fig. 9 for the proper resistor value. The IP1203PBF is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge clock. The free running oscillator frequency is twice the switching frequency. During synchronization, RT is selected such that the free running frequency is 20% below the synchronization frequency. The maximum synchronization frequency that IP1203PBF can accept is 800kHz. Note that the actual switching frequency is half the synchronization frequency.
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IP1203PBF
Overcurrent Protection HICCUP The overcurrent protection function of the IP1203PBF offers a hiccup feature. During overloads, when the overcurrent trip threshold is reached, the power supply output shuts down and attempts to restart (output HICCUP mode). The time duration between the shutdown of the output and the restart is determined by the time it takes to discharge the soft start capacitor. Typically, the discharge time of the soft start capacitor is 10 times the charge time. The duty cycle of the hiccup process is typically 5%. The output will stay in hiccup indefinitely until the overload is removed. The typical overcurrent trip threshold of the device is internally set at 30A. The overcurrent shutdown / HICCUP threshold is about 30% accurate. The IP1203PBF overcurrent shutdown and HICCUP threshold can be set externally by adding ROCSET resistor from OCSET pin. Refer to Fig.8 for ROCSET selection. Overvoltage Protection (OVP) Overvoltage is sensed through output voltage sense pin FBs. The OVP threshold is set to 115% of the output voltage. Upon overvoltage condition, the OVP forces a latched shutdown. In this mode, the upper FET turns off and the lower FET turns on, thus crowbaring the output. Reset is performed by recycling the input voltage. Overvoltage can be sensed by either connecting FBs to its corresponding output through a separate output voltage divider resistor network, or it can be connected directly to its corresponding feedback pin FB. For Type III control loop compensation, FBs should be connected through voltage dividers only. Refer to the IP1203PBF Design Procedure section on how to set the OVP trip threshold. PGOOD This is an output voltage status signal that is open collector and is pulled low when the output voltage falls below 85% of the output voltage. High state indicates that outputs are in regulation. The PGOOD pin can be left floating if not used. Thermal Shutdown The IP1203PBF provides thermal shutdown. The threshold typically is set to 140C. When the trip threshold is exceeded, thermal shutdown turns the output off. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to the normal range.
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IP1203PBF
IP1203PBF Design Procedure
Only a few external components are required to complete a dual output synchronous buck power supply using IP1203PBF. The following procedure will guide the designer through the design and selection process of these external components. A typical application for the iP1203 is: VIN = 12V, VOUT = 1.5V, IOUT = 15A, fsw = 300kHz, Vp-p = = 50mV Setting the Output Voltage The output voltage of the IP1203PBF is set by the 0.8V reference VREF and external voltage dividers.
Vout
Setting the Overvoltage Trip The output of the iP1203 will shut down if it experiences a voltage in the range of 115% of VOUT. The overvoltage sense pin FBs is connected to the output through voltage dividers, R26 and R27 (Fig. 14), and the trip setpoint is programmed according to equation (1). A separate overvoltage sense pin FBs is provided to protect the power supply output if for some reason the main feedback loop is lost (for instance, loss of feedback resistors). An optional 100pF capacitor (C14) is used for delay and filtering. If this redundancy is not required and if a Type II control loop compensation scheme is utilized, FBs pin can be connected to FB. Selecting the Soft-Start Capacitor The soft start capacitor Css is selected according to equation (2): tss = 40 x Css (2)
R2
FB
R5
iP1203
R26
FB S
where, tss is the output voltage ramp time in milliseconds, and Css is the soft start capacitor in F. A 0.1F capacitor will provide an output voltage rampup time of about 4ms. Input Capacitor Selection The switching currents impose RMS current requirements on the input capacitors. Equation (3) allows the selection of the input capacitors.
C14 (Optional)
R27
Fig. 14: Typical Scheme for Output Voltage Setting For Type II compensation, VOUT is set according to equation (1): VOUT = VREF x (1 + R2 /R5 ) (see Fig. 14) (1)
I RMS = I out D(1 - D )
(3)
where, Iout is the output current, and D is the duty cycle and is expressed as: D = VOUT / VIN. For the above example D= 0.13 and, using equation (3) the capacitor rms current yields 5.0A.
Setting R2 to 1K, VOUT to 1.5V and VREF to 0.8V, will result in R5= 1.14 Kohms. Final values can be selected according to the desired accuracy of the output. To set the output voltage for Type III compensation, refer to equation (24) in Type III compensation section.
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IP1203PBF
For better efficiency and low input ripple, select low ESR ceramic capacitors. The amount of the capacitors is determined based on the rms rating. In the above example, a total of 3 x 22F, 2A capacitors will be required to support the input rms current. Output Capacitor CO Selection Selection of the output capacitors depends on two factors: a. Low effective ESR for ripple and load transient requirements To support the load transients and to stay within a specified voltage dip V due to the transients, ESR selection should satisfy equation (4): RESR V / ILoadmax Where, ILoadmax is the maximum load current. If output voltage ripple is required to be maintained at specified levels then the expression in equation (5) should be used to select the output capacitors. RESR Vp-p / Iripple (5) (4) When selecting output capacitors, it is important to consider the overshoot performance of the power supply. If the amount of capacitance is not adequate, then, when unloading the output, the magnitude of the overshoot due to stored inductor energy, and depending on the speed of the response of the control loop, can exceed the overvoltage trip threshold of the IP1203PBF and can cause undesirable shutdown of the output. The magnitude of the overshoot should be kept below 1.125VOUT . To prevent the overshoot from tripping the output a delay can be added by installing capacitor C14 as shown in Fig.14. b. Stability The value of the output capacitor ESR zero frequency fesr plays a major role in determining stability. fesr is calculated by the expression in equation (7). fESR = 1 / (2 x RESR x CO) (7)
Details on how to consider this parameter to design for stability are outlined in the control loop compensation section of this datasheet. Inductor LO Selection Inductor selection is based on trade-offs between size and efficiency. Low inductor values result in smaller sizes, but can cause large ripple currents and lower efficiency. Low inductor values also benefit the transient performance. The inductor Lois selected according to equation (8): LO = Vout x (1 - D) / (fsw x Iripple) (8)
Where, Vp-p is the peak to peak output ripple voltage . Iripple is the inductor peak-to peak ripple current. In addition, the voltage ripple caused by the output capacitor needs to be significantly smaller than the ripple caused by the ESR of the capacitor. Use equation (6) to satisfy this requirement.
Co >
10 2 x f s x RESR
(6)
If the inductor current ripple Iripple is 30% of IOUT1, the 50mV peak to peak output voltage ripple requirement will be met if the total ESR of the output capacitors is less than 11m. This will require 2 x 470F POSCAP capacitors. Additional ceramic capacitors can be added in parallel to further reduce the ESR. Care should be given to properly compensate the control loop for low output capacitor ESR values.
For the above example, and for Iripple of 30% of IOUT, LO is calculated to be 1.0H. The core must be selected according to the peak of maximum output current.
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IP1203PBF
Control Loop Compensation The IP1203PBF feedback control is based on single loop voltage mode control principle. The goal in the design of the compensator is to achieve the highest unity gain (0 db) crossover frequency with sufficient phase margin for the closed loop transfer function. The LC filter of the power supply introduces a double pole with 40db/dec slope and 180 phase lag. The 180 phase contribution from the LC filter is the source of instabilty. The resonant frequency of the LC filter is expressed by equation (9):
Vout
R2
IP1203PBF iP1203
FB
E/A1
R5 VREF C6
CC C9 (Optional)
R19
f LC = 1 / (2 L0 x C 0 )
(9)
The error amplifier of the IP1203PBF PWM controller is transconductance amplifier, and its output is available for external compensation. Two types of compensators are studied in this section. The first one is called Type II and it is used to compensate systems the ESR frequency fesr (equation 7) of which is in the midfrequency range and Type III that can be used for any type of output capacitors and have a wide range of fesr. For output voltage settings less than 1.0V that use low ESR ceramic capacitors, it is recommended that the unity gain crossover frequency be set around 20kHz to maintain stable operation. Type II From Fig.15 the transfer function H(s) of the error amplifier is given by (10): R5 1 + sR19 C 9 H (s) = g m x x (10) R5 + R 2 sR19 C 9 The term s represents the frequency dependence of the transfer function. The Type II controller introduces a gain and a zero expressed by equations (11) and (12):
Magnitude(dB) H(s) dB
FZ
Frequency
Fig. 15: Typical Type II Compensation and its Gain Plot
H ( s) = g m x
R5 x R19 R5 + R 2
(11)
where, gm is the transconductance of the error amplifier.
fz =
Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw.
1 2 x R19 x C 9
(12)
14
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IP1203PBF
2. Calculate R5 using equation (13):
R19 = Vramp x
f xf R + R2 1 1 x 0 2 esr x 5 x (13) Vin f LC R5 gm
Where, VIN = Maximum input voltage f0 = Error amplifier zero crossover frequency fesr= Output capacitor Co zero frequency fLC = Output frequency resonant filter gm= Error amplifier transconductance. Use 2mS for gm. Vramp = Oscillator ramp voltage. Use 1.25V for Vramp 3. Place a zero at 75% of fLC to cancel one of the LC filter poles.
Type III The Type III compensation scheme allows the use of any type of capacitors with ESR frequency of any range. This scheme suggests a double pole double zero compensation and requires more components around the error amplifier to achieve the desired gain and phase margins. Fig. 13 represents the Type III compensation network for IP1203PBF. The transfer function of the Type III compensator is given by equation (17)
H ( s) =
(1 + sR20 C 9 ) x (1 + sR2 C 8 ) 1 x sR2 C 9 (1 + sR20 C 7 ) x (1 + sR21C8 )
C7
Vout
(17)
f z = 0 . 75 x
1 2 Lo x C o
(14)
R20 C8 R21 R2 FB R5 V C6
REF
C9
4. Calculate C9 using equations (12) and (14) Calculation of the compensation components based on the example above, yields: fLC = 5.0kHz fz = 3.8kHz f0 = 45kHz (15% of 300kHz) fesr = 14kHz, per equation (7) using Resr = 12m. R19 = 2.49K C9 = 18nF Sometimes, a pole fp2 is added at half the switching frequency to filter the switching noise. This is done by adding a capacitor Copt in Fig.15 from the output of the error amplifier (CC pin of IP1203PBF) to ground. This pole is given by equation (15):
CC
IP1203PBF iP1203
E/A1
Magnitude(dB) H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
f p2 =
1 2 x R19 x C opt
(15)
Fig. 16: Typical Type III Compensation and its Gain Plot
Copt is found from equation (16) by rearranging the terms in equation (15) and by setting fp2 = fsw / 2:
Copt =
1 2 x f p 2 x R19
(16) 15
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IP1203PBF
The frequencies of the three poles and the two zeros of the Type III compensation scheme are represented by the following equations: fp1= 0 (18) (19) 7. Place the second pole fp2 at or near fesr of the output capacitor Co and determine the value of R21 from R2 equation (19). Make sure R21 <
10
8. Use equation (24) to calculate R5. R 5 = R2 x
V
o
f p2
1 = 2 x R21 x C8 1 2 x R20 x C 7 1 2 x R20 x C 9 1 2 x R2 x C8
V -V
ref
f p3 =
(20)
f z1 = f z2 =
(21)
More than one iteration may be required to calculate the values of the compensation components if crossover frequencies higher than the range specified in step 1 are required (for higher bandwidths and faster transient response performance). To ensure stability a phase margin greater than 45 should be achieved. Refer to AN-1043 for more detailed compensation techniques using Transconductance Amplifiers.
ref
(24)
(22)
The crossover frequency f0 for Type III compensation is represented by equation (23):
f0 =
1 Vramp
x VIN x R20 x C8 x
1 2 x L0 x C 0
(23)
Follow the steps below to determine the feedback loop compensation component values: 1. Select a zero db crossover frequency f0 in the range of 10% to 20% of the switching frequency fsw. 2. Select R20~ 10k 3. Place the first zero fz1 at 75% of the resonant frequency fLC of the output filter. Determine C9 from equation (21). 4. Place a third pole fP3 at or near the switching frequency fSW. Select C7 such that C7 <
C9 10
5. Calculate C8 from equation (23). 6. Place the second zero at 125% of the resonant frequency fLC of the output filter. Calculate R2 using equation (22). 16 www.irf.com
IP1203PBF
Typical Waveforms
Ch1: Switching node, 400kHz Ch2: 800kHz external synchronization
Ch1: Output voltage, 500mV/div Ch3: Output current, 10A/div
Fig. 17: IP1203PBF Outputs Synchronized to 800kHz
Fig. 18: IP1203PBF Output Hiccup, Due to Overload
Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div
Ch1: Output voltage, 100mV/div ac Ch3: Load current, 5A/div
Fig. 19: IP1203PBF Transient Response Load Step 1A to 12A www.irf.com
Fig. 20: IP1203PBF Transient Response Load Step 12A to 0A 17
IP1203PBF
Ch1: FBs input, 200mV/div Ch2: Output voltage, 1V/div
Fig. 21: IP1203PBF Overvoltage Trip. Output Voltage Turns Off When Voltage at FBs Pin Exceeds 15% of FB (0.8V)
18
Fig. 22: IP1203PBF Pin Assignment
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IP1203PBF
Layout Guidelines For stable and noise free operation of the whole power system, it is recommended that the designers use the following guidelines: 1. Follow the layout scheme presented in Fig. 23. Make sure that the output inductor L is placed as close to IP1203PBF as possible to prevent noise propagation that can be caused by switching of power at the switching node Vsw, to sensitive circuits. 2. Provide a mid-layer solid ground plane with connections to the top layer through vias. The PGND pads of IP1203PBF also need to be connected to the same ground plane through vias. 3. To increase power supply noise immunity, place input and output capacitors close to one another, as shown in the layout diagram. This will provide short high current paths that are essential at the ground terminals. 4. Although there is a certain degree of VIN bypassing inside the IP1203PBF, the external input decoupling capacitors should be as close to the device as possible. 5. The feedback track from the output VOUT to FB should be routed as far away from noise generating traces as possible. 6. The compensation components and the Vref bypass capacitor should be placed as close as possible to their corresponding IP1203PBF pins, away from noise generating traces. 7. Refer to IR application note AN-1029 (Optimizing a PCB Layout for an iPOWIR Technology Design) to determine what size vias and copper weight and thickness to use when designing the PCB. 8. Place the overcurrent threshold setting resistors ROCSET close to the IP1203PBF block at the corresponding connection node.
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Fig. 23: IP1203PBF Suggested Layout
19
IP1203PBF
10uF 16V
10uF 16V
10uF 16V
PGND
PGND
2
3
4
5
7
17
20
21
PGND PGND PGND PGND PGND PGND
20
U1
J1
1 23
37.4K
12V
VIN
C18 R1
10K
V IN
10uF 16V
C16
C17
C19
J2
24
1.0uH
VIN VIN V INS
ROCSET ROCSET
18 19
470uF 6.3V
OCSET
16
PGND
VINS V INS VSW
V SW L1
C10
1.5V
470uF 6.3V
PGOOD13 V CC_bypass 6
22
PGOOD VCC_bypass VSWS
VSWS
C11
C13
0.1uF
C4
2.2uF
SS
8 10
0.1uF
SS
FB
FB
R2 R20
NI 1K
C5
IP1203PBF
iP1203
CC
9
R21 C7
NI NI
C8
NI
V
REF 14
C6
100pF
VREF
Compensation Configuration
0.018uF
C9
CC
R19
2.49K
R5
1.13k
Designator
Type II Configuration Type III Configuration
SYNC 15
Installed Installed Removed
12
SYNC
Type III Compensation
R20,R21
Removed
C7, C8
Removed
Fig. 24: Typical Application Schematic
RT
R19
Installed
RT
FBS
11
FBS
C14
100pF
R26 R27
1.13K 1K
30.9K(300kHz)
R24
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IP1203PBF
0.15 [.006] C 2X 6 T OP VIEW 9 [0.355] B A S IDE VIEW 2.31 [.0909] 2.13 [.0839] NOT ES : 1. 2. 3. 4. 5 6 DIMENS IONING & TOLERANCING PER AS ME Y14.5M-1994. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. CONT ROLLING DIMENS ION: MILLIMET ER LAND DES IGNATION PER JES D MO 222, S PP-010. PRIMARY DAT UM C IS S EAT ING PLANE.
ORIENT AT ION CORNER ID 7 9 [0.355]
BILAT ERAL T OLERANCE ZONE IS APPLIED TO EACH S IDE OF T HE PACKAGE BODY. 7 DET AILS OF T ERMINAL # 1 IDENTIFIER ARE OPT IONAL, BUT MUS T BE LOCAT ED WITHIN T HE ZONE INDICAT ED . THE T ERMINAL # 1 IDENT IFIER MAY BE EIT HER A MOLD OR MARKED FEAT URE .
e
0.889
X Y X Y X Y X Y X Y X Y X Y X Y X Y R K
(1)
0.508 0.800 0.508 0.800 2.769 1.778 2.261 2.261 1.016 0.508 1.016 2.139 1.016 2.261 2.032 2.261 1.524 2.032 0.269 0.254
0.15 [.006] C 2X 6.474 4.966 3.835 3.353 2.959 1.791 1.422 0.914 0.000 9.000 8.369 7.633 6
(2) (3) (4) (5)
0.000 0.758 0.892 1.380 1.833 1.870 3.021 4.243 4.461 4.522 7.489 8.352 9.000 BOT T OM VIEW
(6) (7) (8) (9) (10)
15X K 15X R 12X e
LAYOUT NOTES : 1. MIRROR T HE EXACT LY MODULE PAD OPENING TO PCB LAYOUT .
Fig. 25: Outline Drawing Refer to the following application notes for detailed guidelines and suggestions when implementing iPOWIR technology products: AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1043: Stabilize the Buck Converter with Transconductance Amplifier This paper explains how to stabilize a buck converter for Type II and Type III control loop compensation using transconductance amplifiers. AN-1047: Graphical solution to two branch heatsinking Safe Operating Area This paper is a suppliment to AN-1030 and explains how to use the double side Power Loss vs Current and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifiers iPOWIR Technology BGA and LGA Packages This paper discusses optimization of the layout design for mounting iPOWIR BGA and LGA packages on printed circuit boards, accounting for thermal and electrical performance and assembly considerations. Topics discussed includes PCB layout placement, routing, and via interconnect suggestions, as well as soldering, pick and place, reflow, cleaning and reworking recommendations. www.irf.com 21
IP1203PBF
0438 XXXX iP1203 IP1203PBF
0438 XXXX iP1203 IP1203PBF
0438 XXXX iP1203 IP1203PBF
16.0 (.630)
12.0 (.472)
FEED DIRECTION NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. iP1203, IP1203PBF BGA
Fig. 26: Tape & Reel Information
NOT ES : 1. OUT LINE CONFORMS T O EIA-481 & EIA-541. IP1203PBF, BGA
0538 XXXX IP1203PBF
Fig. 27: Part Marking
22
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IP1203PBF
SQUEEGEE VIEW RECOMMENDED STENCIL OPENING ALL DIMENSIONS IN INCHES The recommended reflow peak temperature is 260C. The total furnance time is approximately 5 minutes with approximately 10 seconds at the peak temperature. Fig.28: Recommended Solder Profile and Stencil Design
This product has been designed and qualified for the industrial market.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice.8/06 www.irf.com 23

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